Community

AES Convention Papers Forum

32-Bit SIMD SHARC Architecture for Digital Audio Signal Processing Applications

Document Thumbnail

This paper examines desirable DSP architectural features to consider for implementation of real time audio applications using a 32-bit Single Instruction Multiple Data (SIMD) DSP based on a Modified Harvard Architecture. This discussion will examine the specific features in this architecture that are desirable for implementing many of today's professional and consumer audio equipment. The first topic covered are the important audio processor-specific characteristics of this SIMD architecture such as data word size, dynamic range/SNR capabilities, memory organization, processor speed, benchmarks and I/0 capabilities. Part Two will highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture which can speed up DSP execution by as much as a factor of 5 over earlier SISD SHARC: architectures.

Authors:
Affiliation:
AES Convention: Paper Number:
Publication Date:
Subject:

Click to purchase paper as a non-member or you can login as an AES member to see more options.

No AES members have commented on this paper yet.

Subscribe to this discussion

RSS Feed To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.

Start a discussion!

If you would like to start a discussion about this paper and are an AES member then you can login here:
Username:
Password:

If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.

AES - Audio Engineering Society