This paper examines the performance and implementation costs of various filter topologies using fixed and floating-point arithmetic, and paying attention to scaling, quantization noise, coefficient sensitivity, limit cycles, and overflow oscillations. The fractional and integer word-length requirements for various topologies are mathematically simulated. Optimal MAC units for specific topologies in terms of performance and cost are suggested.

Authors: Clark, Rob J.; Ifeachor, Emmanuel C.; Rogers, Glenn M.
Affiliations: University of Plymouth, Devon, UK ; Allen & Heath Limited, Penryn, Cornwall, UK ; University of Plymouth, Devon, UK (See document for exact affiliation information.)
AES Convention: 99 (October 1995) Paper Number: 4100
Publication Date: October 1, 1995
Subject: Digital Signal Processing

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