An IC that combines the functions of an AES/EBU receiver and asynchronous rate converter has been designed. This IC allows the systems designer to receive an external AES/EBU signal and sync it to an internal crystal-controlled system clock. The IC uses an all-digital AES receiver that can tolerate large amounts of jitter and tracks over a wide and continuous range of sample frequencies. The sample-rate converter uses a new algorithm that employs a noise-shaped clock signal in conjunction with a digital interpolator/decimator.

Authors: Adams, Robert; Nguyen, Khiem; Sweetland, Karl
Affiliation: Analog Devices Semiconductor Inc., Wilmington, MA
AES Convention: 103 (September 1997) Paper Number: 4536
Publication Date: September 1, 1997
Subject: Signal Processing and Conversion

Click to purchase paper as a non-member or you can login as an AES member to see more options.

No AES members have commented on this paper yet.

Subscribe to this discussion

To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.

Start a discussion!

If you would like to start a discussion about this paper and are an AES member then you can login here:
Username:
Password:

If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.