A single CMOS chip has been realized which includes two 16-bit A/D converters and four 16-bit D/A converters. Also included is an adjustable input gain section, as well as an adjustable output level section. An on-chip PLL allows the device to be clocked by an audio sample rate clock (for example 44.1 kHz). Topics discussed include design trade-offs in filter performance to achieve low cost, and novel techniques used to achieve a low-jitter integrated PLL.

Authors: Harris, Steven; Scott, Jeff; Krone, Andy; Lin, Shao-Chyi
Affiliation: Crystal Semiconductor Corporation, Austin, TX
AES Convention: 94 (March 1993) Paper Number: 3588
Publication Date: March 1, 1993
Subject: Digital Signal Processing

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