A high-performance jitter-reduction circuit based on high-order phase-locked-loop technique has been built for digital audio. It provides over 40-dB attenuation for midfrequencies but still maintains over 10-Hz cutoff frequency. By employing a crystal-based voltage-controlled oscillator, very low intrinsic jitter is achieved.
Author:
Wong, Wai-Ki
Affiliation:
City Polytechnic of Hong Kong, Hong Kong
AES Convention:
97 (November 1994)
Paper Number:
3888
Publication Date:
November 1, 1994
Subject:
Analog Signal Processing
Click to purchase paper as a non-member or you can login as an AES member to see more options.
No AES members have commented on this paper yet.
To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.
If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.