The DSP engine design uses a configurable array of processors running identical basic programmes, controlled from a host PC and allocated by software according to simulation requirements.
Authors:
Brookes, D. M.; Harris, R. I.; Wilson, R. J.
Affiliations:
Imperial College, London, UK ; KEF Electronics, Maidstone, Kent, UK(See document for exact affiliation information.)
AES Convention:
90 (February 1991)
Paper Number:
3057
Publication Date:
February 1, 1991
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