Sample and Hold circuits are widely used in digital audio-systems and generally in signal processing and data conversion systems. High resolution analog-to-digital and digital-to-analog conversion modules require S&H-circuits for track-and-hold and deglitching. Sample and Hold circuits can cause various types of audio signal degradation: Aperture time is a (nonlinear) function of residual charge in the hold circuit; the error (clock jitter) and too short sampling intervals result in amplitude errors, the magnitude of this error increases with approaching the samplilng bound; Finite sampling pulse duration effects in conjunction with the order of the sample and hold circuit (zero- or first-order or polygonal hold) a frequency dependent transfer characteristic; Input-to-output and control-to-outut crosstalk causes additional errors. Most circuits apply MCSFETs for the sampling gate and the hold amplifier input stage, which limits the large signal characteristics and causes temperature effects. Design philosophy of sample and hold circuits requires a careful consideration of each possible error source.
Authors:
Pichler, Heinrich; Skritek, Paul
Affiliation:
Technical University Vienna, Institut fuer Allgemeine Elektrotechnik, Austria
AES Convention:
65 (February 1980)
Paper Number:
1584
Publication Date:
February 1, 1980
Click to purchase paper as a non-member or you can login as an AES member to see more options.
No AES members have commented on this paper yet.
To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.
If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.