An efficient method to linearize the switching (power) stage of open-loop class D amplifiers is presented. This technique has been successfully applied to an open-loop fully-digital PWM class D amplifier designed in a 40 nm CMOS process leading to nearly 15 dB improvement in the Total Harmonic Distortion (THD). Simulated open-loop class D amplifier performance resulted to 105 dBA Signal-to-Noise Ratio (SNR), and 1W output power over 8 Ohm with 90% power efficiency and 0.014% THD.

Authors: Guanziroli, Federico; Confalonieri, Pierangelo; Nicollini, Germano
Affiliation: STMicroelectroics, Milan, Italy
AES Convention: 140 (May 2016) Paper Number: 9484
Publication Date: May 26, 2016
Subject: Audio Equipment and Audio Formats

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