This paper presents a real-time power supply noise correction technique in a fully-digital class D audio amplifier. The power supply is scaled and applied to a 12-bits Nyquist ADC to modify the amplitude of the Pulse-Width-Modulator reference carrier. An improved supply extrapolation algorithm results to a power supply rejection from one to two orders of magnitude higher than reported implementations. Class D sensitivity to clock jitter is presented. SNR higher than 100dBA have been measured in the presence of both power supply ripple and clock jitter. The PWM and output stage are integrated in the same chip in a 0.13µm digital CMOS technology, whereas an external ADC has been used to demonstrate the validity of the supply-feedback algorithm.

Authors: Bassoli, Rossella; Guanziroli, Federico; Crippa, Carlo; Nicollini, Germano
Affiliation: ST-Ericsson, Monza Brianza, Italy
AES Convention: 135 (October 2013) Paper Number: 8968
Publication Date: October 16, 2013
Subject: Amplifiers

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