For live digital audio systems with high-resolution multichannel functionalities, it is desirable to have accurate latency control and estimation over all the stages of digital audio processing chain. The evaluation system we designed supports 12 channel, 24 bits Sigma Delta based ADC/DAC, incorporating both a programmable FPGA and a Digital Signal Processor. It can be used for testing and evaluation of different ADC/DAC digital filter architectures, audio sample buffer subsystem design, interrupt and scheduling, high level audio processing algorithm and other system factors, which might cause the latency effects. It also can estimate the synchronization and delay of multiple channels.

Authors: Wang, Yonghao; Zhu, Xiangyu; Fu, Qiang
Affiliations: Birmingham City University, Birmingham, UK; Queen Mary University of London, London, UK; Hebei University of Science and Technology, Shijiazhuang, China; Shijiazhuang Mechanical Engineering College, Shijiazhuang, China(See document for exact affiliation information.)
AES Convention: 132 (April 2012) Paper Number: 8678
Publication Date: April 26, 2012
Subject: Audio Equipment and Instrumentation

Click to purchase paper as a non-member or you can login as an AES member to see more options.

No AES members have commented on this paper yet.

Subscribe to this discussion

To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.

Start a discussion!

If you would like to start a discussion about this paper and are an AES member then you can login here:
Username:
Password:

If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.