This paper details the design and implementation of a novel S/PDIF transceiver with a very low jitter bandwidth. We describe and demonstrate a system based on multiple-loops that synchronises to the incoming data stream with a very low bandwidth and provides the original data unmodified on a clean low jitter output clock without the need for a sample rate converter. Thus we eliminate any jitter above a low frequency (typically 10Hz) on the input data and also avoid any distortion caused by sample rate converters.
Author:
Lesso, Paul
Affiliation:
Wolfson Microelectronics
AES Convention:
121 (October 2006)
Paper Number:
6948
Publication Date:
October 1, 2006
Subject:
Amplifiers & High Resolution
Click to purchase paper as a non-member or you can login as an AES member to see more options.
No AES members have commented on this paper yet.
To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.
If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.