High performance DSPs have been used extensively for the implementation of signal transforms in transform based audio coders. While the first generation of DSPs featured single stage MAC (Multiple Accumulate) blocks, the current generation of DSPs feature dual-MAC hardware blocks. Though fast algorithms are available for implementation of transforms, a re-look at the algorithms from this semi-parallel architecture point of view is beneficial as it leads to more efficient implementations. This paper looks specifically at the family of lapped transforms, and quantifies the implementation efficiency of traditional fast optimizations on architectures with this type of semi-parallel computing capability, and derives algorithmic methods of increasing this efficiency.
Author:
Sundareson, Prabindh
Affiliation:
Digital Audio Group, Texas Instruments India, Bangalore, Karnataka, India
AES Convention:
112 (April 2002)
Paper Number:
5614
Publication Date:
April 1, 2002
Subject:
Signal Processing Forum
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