AES Convention Papers Forum

This design falls into a common trap in that it presumably has a "balanced" input connection at points in the schematic shown as plus and minus. First, there is no requirement for signals on a balanced line to be symmetrical (equal and opposite voltage swings). Second, a prime requirement for a balanced input stage is that it have a differential stage, i.e., one that rejects common-mode voltage. Worse yet, the "dual single-ended" approach delivers common-mode input voltage, in-phase, to both output tubes. Therefore, both output tubes will see only the DCR and leakage inductance between halves of the primary as a load, potentially resulting in extraordinarily high plate currents for both. This will cause rather nasty distortions as the tubes are pushed into very non-linear territory. Bottom line: the most important duty of a balanced input is to remove common-mode voltage. Any real-world system interconnection will have some common-mode (ground voltage differences being the main source) noise to be rejected.

This whole notion is based on the myth that voltage symmetry in balanced lines is responsible for its noise rejection property. It is the matching of line impedances (with respect to ground) that define a balanced interface - as stated in the "informative annex" of IEC 60268-3 (balanced inputs and outputs).