AES Conference Papers Forum

Discrete-time Modeling of Continuous-time Pulse Width Modulator Loops

Document Thumbnail

Continuous-time feedback loops are very popular in the design of class-D power amplifiers where an analog signal is converted to a high power pulse-stream feeding the load. Such loops embed a continuous-time loop filter network, a comparator and a switching power stage. The loop is either synchronized by injection of a carrier signal (e.g. triangle or sawtooth waveform) or is free-running (self-oscillating). Traditionally, the dynamics of these loops are analyzed by using linearized continuous-time models where the comparator is modeled as a gain. However, this method fails to accurately explain several important characteristics such as noise aliasing, image components and loop stability. This paper analyses the sampling nature of the comparator and derives a general linear discrete-time loop small-signal model which can be applied to loops of any order. An important conclusion is that the comparator gain only depends on the slope at zero crossings and not of the amplitude of the comparator input signal. In addition, the model shows important differences between synchronized and free running loops which is demonstrated on simple 1st–order cases.

AES Conference:
Paper Number:
Publication Date:

Click to purchase paper as a non-member or you can login as an AES member to see more options.

No AES members have commented on this paper yet.

Subscribe to this discussion

RSS Feed To be notified of new comments on this paper you can subscribe to this RSS feed. Forum users should login to see additional options.

Start a discussion!

If you would like to start a discussion about this paper and are an AES member then you can login here:

If you are not yet an AES member and have something important to say about this paper then we urge you to join the AES today and make your voice heard. You can join online today by clicking here.

AES - Audio Engineering Society